AT89C5131

The mobile storage device with USB2.0 controller chip AT89C5131 TI Corporation, the data storage medium with SAMSUNG's NAND FLASH chip K9K2G08U0A. 2.1 AT89C5131 chip features ATMEL AT89C51-12QC is produced by high-performance core based on 80C52 full speed USB controller built-in 8-bit single CPU micro-processing chip [2], directly compatible with MCS-51 series, its internal integrated 32KB of Flash memory, available in the IN-System Programming; built-in 4KB EEPROM, which 1KB for user data storage, with a control port, and six general programmable ports, and supports control transfer, synchronous transmission, interruption of transmission and bulk transfer of four transfers way. The chip has the advantage of developers familiar with the structure and instruction set, processing ability, constitute the system of the circuit is simple, convenient debugging. 2.2 K9K2G08U0A chip features K9K2G08U0A total capacity of the memory chip (256M +8192 k) bit * 8bit, 2048 is divided into sectors, each sector is divided into 64 pages, each page in addition to 2k bytes of main storage area, but also include 64 spare bytes [3]. It 200μs / complete 2112-byte page programming operation; also completed 128k bytes in 2ms erase operation; while randomly reading time is 25μs; data lines and address lines multiplexed to I/O0-I/O7 A total of eight lines; also provides a command-control signals are line; data retention for more than 10 years. NAND FLASH memory will not increase the storage capacity increases the number of pins, which greatly facilitate the system design and product upgrading, but the chip connection methods and programming to access the same memory than the traditional big difference there. 2.3 Hardware Schematic The hardware part of the built-in USB controller, microcontroller AT89C5131, SAMSUNG's NAND FLASH chip K9K2G08U0A composition, hardware schematics shown in Figure 1. Must write the corresponding command to the successful implementation of the various flash memory operation, because the data lines and address lines multiplexed to eight lines, the address, command and data input / output through the command latch signal (CLE) and address of the lock survival signal (ALE) to jointly control the time division multiplexing. I / O [7:0]: Data I / O port, the signal and AT89C5131 chips P0 [7:0] connection. : Write enable signal. In its rising edge, the command, address and data latched to the corresponding register. The signal and AT89C5131 chips P3.6 signal connections. : Read enable signal. In its falling edge, the output data to I / O bus, the same time, it can accumulate on the internal data address. The signal and AT89C5131 chips P3.7 signal connection. CLE: Command latch enable signal. When CLE is high, the command in rising through the I / O port into the command register. The signal and AT89C5131 chips P1.0 pin connection. ALE: Address latch enable signal. When ALE is high, the address into the address register at the rising edge. The signal and AT89C5131 chips P1.1 pin connection. : Chip select signal. Used to control equipment selection. When the device is busy is high and is ignored, when in device programming and erase operations can not return to standby. The signal and AT89C5131 chips P1.2 pin connection. R /: ready / busy output. When it is low, said the program, erase and random read operation is in progress, the operation is completed and returned to high; when the chip select or output not being prohibited, their time is high. The signal and AT89C5131 chips P1.3 pin connection.