This design uses a current control mode pulse width modulation. The whole working process is the exchange of input by the filter, rectified into a DC high voltage, then switch chopper, after high-frequency step-down transformers are high frequency rectangular voltage, and finally through the output rectifier obtain the required DC voltage. System requirements on the switching power supply is the AC input voltage range of 90 ~ 270 V, it can output +5 V (power supply as the control part) and 12 ~ 60 V (main circuit) voltage. Output current of 1 ~ 3 A. 2.2 Microcontroller Circuit Design
MCU control circuit is composed of MCU AT89S52, ADC (TLC0832), multi-selector switch (CD4051), digital potentiometers (X9C102), digital temperature sensor DSl8820, sampling resistor Rs and Rw, 2 × 4 keyboard, LCD (CONl6), etc. composition. This part of the design should be the first under the battery model parameters corresponding to the keyboard design of the charge current, charge voltage and charge time, when the circuit connected to the battery, the charging process begins, then by the MCU by detecting the battery voltage sampling resistor RM If the detected battery voltage is lower than normal because of the scope of the transitional discharge Er Shi. So, in order to avoid excessive charge current damage caused by batteries, should first implement a stable low current battery charge (in this design process set l / 5 of the set charging current), while SCM start time, after the microcontroller will continue to test battery voltage and charge current and displayed on the LCD screen, with the charge to the battery voltage rise, when up to normal range, the microcontroller can control the digital potentiometer to adjust output voltage, high current constant current to turn charge (that is, setting current) way, then, has remained constant SCM test the battery voltage, when the voltage reaches the set value, the SCM to issue an order to increase the digital potentiometer's resistance, and reduced by pulse-width modulation output voltage. Thereby reducing the charge current when the charge current is reduced to 1 / 5 to set the current time, and then to trickle charge, charge time to finally turn off the power, thus avoiding excessive temperature rise due to the battery or serious charge polarization affect quality, improve battery life. When the detected battery voltage, charge current and temperature exceeds a set value of 1 / 10 times (set by the program), microcontroller output alarm signal alarm immediately. At the same time to relay and cut off the mains, to improve the safety and reliability of charge.
Display can be used to display real-time sampling to the single chip battery voltage, charge current, charge time and battery have been the temperature, the keyboard is used to set the charging voltage (charging limit voltage), constant charge current (charge current limit) and the charging time. Circuit in the microcontroller through the serial port RS232 and PC connected to the virtual display is used to store data and charging parameters settings. When the detected charge current is zero, the microcontroller into sleep mode. When the detected charge current is not zero, the microcontroller is activated. 2.3 PWM Controller
PW M Controller UC3842 is the core part. UC3842 chip with 5.0 V reference voltage regulator, high gain error amplifier and pulse width of the comparator, it can control the drive chip. The drive can provide 25 mA of output current. Can directly drive NOSFET adjustment control to adjust the charger output voltage and current. Since the drive also features over-current, over-voltage protection, supply voltage can be 8 ~ 40 V, while the starting current is less than 1 mA, operating temperature for the O ~ 70 ℃, which is the ideal new pulse-width modulator. The PWM controller at startup, by R1, Rw. To provide for the UC3842AD start voltage, let it work, its auxiliary winding terminal voltage of 3,4 rectified by D1, C4, C5 filter, DW1 after regulators received 16 V DC voltage, all the way to 7 feet for added power UC38427 another pass digital potentiometers R3 and after the partial pressure of added UC3842 X9C102 2 feet. As a PWM input signal. Generally in the design of such power, the output voltage sampling of the supply voltage can be connected with the UC3842. In order to reflect changes in output voltage, this design does not increase regulator, but this will work UC3842 voltage instability, the output harmonic components increased, in order to overcome this shortage, the design of the power supply voltage used by the UC3842 winding 3,4 side pressure single rectifier, filter, regulator, he has provided to the stability of UC3842 voltage 16 V-chip. Regulation of charging voltage is the battery voltage by the outer voltage sampling circuit R12, RM sampling, multi-electronic switch via options, MD transform, single chip processing, into the digital potentiometer, digital potentiometers to control the effective resistance. Indirectly control the UC3842 voltage of 2 feet, then control the pulse duty cycle to change the charging voltage. When the charger output voltage is high, the feedback back to 2 feet UC3842 voltage higher (than the reference voltage of 2.5 V), the drive signal of the pulse duty cycle decreases, the output voltage drops, so as to achieve the purpose of regulation. Charge current is regulated by a first charge current sampling resistor Rs by the outer current sampling and LM358 amplified (R1 adjust magnification available), multi-electronic switch to select, MD transform, sending single chip processing, and then adjust the resistance of digital potentiometer . The adjustment process and the voltage regulator similar, in fact, current regulation is achieved through the voltage regulator.
2010年5月19日星期三
2010年5月18日星期二
SA8282/IG/DP1S中文资料
ADO～AD7：8位地址与数据复用总线，用于从微处理器接收地址与数据信息；??? ：此3个引脚为Intel(Motorola)控制模式；SA8282在工作时可自动适应Intel或Motorola控制模式，当ALE(AS)管脚变为高电平时，SA8282内部检测电路将自动锁存RD(DS)线上的状态，如果检测结果为低电平，则采用MO-TOROLA控制模式；如果检测结果为高电平，则采用Intel控制模式；?? ：复位端，低电平有效；?? ：片选输入，该控制线可使SA8282与其他外围接口芯片共享同一组总线。??? RPHT，RPHB，YPHT，YPHB，BPHT，BPHB：标准TTL电平输出端口(即PWM驱动信号)，可分别驱动三相逆变器的6个功率开关器件；??? ：输出封锁状态指示，用于表明输出是否被锁存，低电平有效；??? SETTRIP：关断触发信号输入端，当输入为高时，TRIP及6个PWM输出端将被迅速锁存在低电平状态，且只有在RST复位时才能解除；??? WSS：波形采样同步端口；??? ZPPB，ZPPY，ZPPR：分别是三相信号的零相位脉冲输出端；??? CLK：时钟信号输入端；??? VDD：+5 V偏置电源；??? VSS：接地端。1．2 主要特点??? (1)全数字化。SA8282与微处理器相连时，可自动适应Intel和Motorola两种总线接口，而且编程简捷方便。它的全数字化脉冲输出具有很高的精度和稳定性。??? (2)工作方式灵活。SA8282具有6个标准的TTL电平输出端，可以驱动逆变器的6个功率开关器件。电路的载波频率、调制频率、调制比、最小脉宽、死区时间等工作参数均可直接通过软件设定，而不需要任何外接电路，从而降低了硬件成本。??? (3)工作频率范围宽、精度高。SA8282的三角载波频率可调，当时钟频率为12．5 MHz时，载波频率最高可达24 kHz，输出调制频率最高可达4 kHz，输出频率的分辨率为12位。
?
2 硬件设计??? 由SA8282构成的三相变频变压电源电路结构图如图2所示，是SA8282与单片机AT89C51连接应用电路。
??? 传送控制参数后，判断SA8282/IG/DP1S允许输出，则开始输出SPWM控制信号，逆变器开始工作。工作过程中，单片机不断地处理检测反馈回来的信号，控制SA8282调整输出的SPWM控制信号，控制系统的输出状态，以满足系统的性能要求。在系统正常工作过程中，不断更新看门狗定时器。防止其溢出而中断SPWM控制信号的输出。初始化程序，实现键盘处理、刷新处理与下位机和其他程序主要完成硬件器件工作方式的设定、系统运行参数和变量的初始化等。
?
2 硬件设计??? 由SA8282构成的三相变频变压电源电路结构图如图2所示，是SA8282与单片机AT89C51连接应用电路。
??? 传送控制参数后，判断SA8282/IG/DP1S允许输出，则开始输出SPWM控制信号，逆变器开始工作。工作过程中，单片机不断地处理检测反馈回来的信号，控制SA8282调整输出的SPWM控制信号，控制系统的输出状态，以满足系统的性能要求。在系统正常工作过程中，不断更新看门狗定时器。防止其溢出而中断SPWM控制信号的输出。初始化程序，实现键盘处理、刷新处理与下位机和其他程序主要完成硬件器件工作方式的设定、系统运行参数和变量的初始化等。
2010年5月16日星期日
Development of Industrial EthernetFigure
Development of Industrial EthernetFigure 1 is from the ARC Advisory Group's market data. ARC forecasts in the next few years, industrial Ethernet market will grow strongly. Which, in the 2011 Industrial Ethernet devices and switch sales compound annual growth rate of 30%
Figure 1 ARC Advisory Group forecasts: the next five years, Ethernet switches, field devices and the annual compound growth of 30%
The current industry is not unified communications environment, more competitive industrial Ethernet standard and traditional field bus standard, a lot of solutions using ASIC, ASSP and MCU to achieve. Such hardware is not very flexible, we need to support each user to change the hardware and the corresponding protocol stack software
Currently, there are several open standards for industrial Ethernet protocols, including EtherCAT, Ethernet IP, Modbus / TCP, PROFINET, Ethernet POWERLINK and SERCOS III. These protocols use a single hardware design can be realized in the FPGA, so that engineers can support multiple protocols in a standard hardware platform standardization
Industrial Ethernet solution supports a common platform, thus promoting the integration of office and factory, in the bottom of the controller and the link between plant management, real-time information sharing to achieve rapid response. Also available through the Intranet to connect the internal workshop, workshop and office and between the workshop between the real-time and non real-time systems, field bus protocol and the corresponding backward compatible to support new systems and old systems platform for action.
Open protocol standards simplifies the implementation and network communications equipment to help plant the transition from the field bus to a single multi-layer Ethernet, support a variety of commercial equipment and cables, even if industrial Ethernet protocol has changed, it can be reused The equipment and cables.
Industrial Ethernet protocol architecture can be divided into three categories (Figure 2): A class, B class and C class of protocol standards. A class using a standard Ethernet TCP / IP, primarily for non-real-time information-level applications such as factory automation, speed sensors and display PLC HMI applications. The typical response time is about 100ms or so, or longer. EtherNet / IP, Modbus / TCP and PROFINET CBA is common in this type of Ethernet protocol. B class uses standard Ethernet hardware, custom software stack on top of and provide appropriate real-time performance, response time less than 10ms. Class B for low-precision motor control and remote I / O communications applications involving the Ethernet Powerlink and PROFINET RT and other agreements. C class in the MAC layer using the improved hardware, ON-Semiconductor also determined using custom software to achieve fast real-time performance, generally less than 1ms, applied to the device level of precision motion control applications. EtherCAT, PROFINET IRT and SERCOS III C class industrial Ethernet protocols are examples. C class architecture standard network traffic bandwidth is less than A class architecture. Industrial Ethernet to support all three types of architecture, needs to have a comprehensive configurable platform capabilities, can also change the hardware and software
Figure 1 ARC Advisory Group forecasts: the next five years, Ethernet switches, field devices and the annual compound growth of 30%
The current industry is not unified communications environment, more competitive industrial Ethernet standard and traditional field bus standard, a lot of solutions using ASIC, ASSP and MCU to achieve. Such hardware is not very flexible, we need to support each user to change the hardware and the corresponding protocol stack software
Currently, there are several open standards for industrial Ethernet protocols, including EtherCAT, Ethernet IP, Modbus / TCP, PROFINET, Ethernet POWERLINK and SERCOS III. These protocols use a single hardware design can be realized in the FPGA, so that engineers can support multiple protocols in a standard hardware platform standardization
Industrial Ethernet solution supports a common platform, thus promoting the integration of office and factory, in the bottom of the controller and the link between plant management, real-time information sharing to achieve rapid response. Also available through the Intranet to connect the internal workshop, workshop and office and between the workshop between the real-time and non real-time systems, field bus protocol and the corresponding backward compatible to support new systems and old systems platform for action.
Open protocol standards simplifies the implementation and network communications equipment to help plant the transition from the field bus to a single multi-layer Ethernet, support a variety of commercial equipment and cables, even if industrial Ethernet protocol has changed, it can be reused The equipment and cables.
Industrial Ethernet protocol architecture can be divided into three categories (Figure 2): A class, B class and C class of protocol standards. A class using a standard Ethernet TCP / IP, primarily for non-real-time information-level applications such as factory automation, speed sensors and display PLC HMI applications. The typical response time is about 100ms or so, or longer. EtherNet / IP, Modbus / TCP and PROFINET CBA is common in this type of Ethernet protocol. B class uses standard Ethernet hardware, custom software stack on top of and provide appropriate real-time performance, response time less than 10ms. Class B for low-precision motor control and remote I / O communications applications involving the Ethernet Powerlink and PROFINET RT and other agreements. C class in the MAC layer using the improved hardware, ON-Semiconductor also determined using custom software to achieve fast real-time performance, generally less than 1ms, applied to the device level of precision motion control applications. EtherCAT, PROFINET IRT and SERCOS III C class industrial Ethernet protocols are examples. C class architecture standard network traffic bandwidth is less than A class architecture. Industrial Ethernet to support all three types of architecture, needs to have a comprehensive configurable platform capabilities, can also change the hardware and software
2010年5月13日星期四
The system uses distributed control network, divided into upper and lower machine two parts, the host computer hardware, including CAN communications adapter and the host machine monitoring and management component; lower machine by the CAN nodes and in situ sensors group and the control of temperature and humidity parameters device component, shown in Figure 1.
By adjusting the Ral7, Ral8 and Ral9 size, get a larger resistance. However, the process of debugging, we have observed for the measurement time extension Shuchurengran Hui moved to saturation, for which we took advantage of a first-order part with Xiang Ji Fen out the output of the DC component, feedback to Ral9 the end, the formation of self Gensui Network , as shown in the left portion of Figure 2. Use to select the integration capacitor leakage current is relatively small, drift is small, relatively stable performance of the capacitor, the amplifier to select the high gain, high input impedance, low bias current, low drift operational amplifiers, can guarantee the performance of the charge amplifier.
In the application of active vibration control real interest to the signal frequencies are in between 0.5 ~ 200Hz, In order to filter low-frequency drift and unnecessary high-frequency signal, we design a five-order Bessel (Bessel) Di Tong Hu a first-order high-pass band-pass filter composed of five order Bessel low pass it by two second-order low-pass and a first-order low-pass form, their parameters are: passband gain of a cut-off frequency of 475Hz , Q value of 0.577; pass band gain of a cut-off frequency of 565Hz, Q values of O. 737; pass band gain of a cut-off frequency of 530Hz, one, two second-order low-pass circuit by the unity gain KRC. ??? Signal into the DSP's ADC should be preceded by the addition circuit to adjust the ratio to between 0 ~ 3V, 0V, or lower than 3V DSP have damaged the danger of this we have added a limit protection circuit
In this paper, MAX547 as the core component of the F2812 design and implementation of the D / A converter circuit. MAX547-house contains eight 13-bit voltage output D / A converters have an input before each DAC latch and the DAC latch, can be separately gated, to 8 D / A converter. Two DAC per share a reference voltage, a total of four independent external reference voltage. MAX547 interface signal has three address lines, respectively, eight-channel addressing options, 13-bit data line, a chip select / CS, Write / WR, asynchronous input / LD and clear / CLR and other control signals, control signals are level triggered. These interface signals are with the TTL / CMOS level matching, it directly with the MAX547 F2812 connected without the need for level translation. MAX547 is a ± 5V dual supply, the output voltage swing of -4.5 V ~ 4.5V. ??? When the MAX547's write signal / WR and the chip select signal / CS are low, and A0, A1, A2 Address signal is valid, the corresponding channel input latch open, read the conversion values from the data line , when / WR, and / CS goes high one, the data will be locked into the corresponding input latch. / LD is responsible for switching DAC latch, when the / LD is low, DAC latch open, the data from the input latch into the DAC latch, when the / LD becomes high, the data will be maintained in DAC Latch device, the count by the DAC to analog conversion. When / LD, / WR and / CS are low, the data can be directly transmitted to DAC latch, but the / LD should be higher than / WR high inversion delay 50ns. / CLR, you can convert the contents of the DAC is set to 1000H, AGND to the analog output voltage. ??? F2812 has the external interface (XINTF), can the image of five independent external storage space, each storage space has a chip select signal. 8 channels to MAX54.7 address assignment in an external storage area 0, through an external interface bus connection with the F2812 shown in Figure 4. To start the MAX547 internal DACA, DACB, DACC, DACD, DACE, DACF, DACG, DACH carry out a number - analog conversion, respectively, to address D9H, B2H, B3H, F4H, F5H, 7EH, 7FH write the data that need to be converted be. For MAX547AEQH need four independent reference voltage, the system uses a precision voltage reference provides a standard chip REF02 voltage, after four buffered voltage follower. REF02 5V output standard voltage, after conversion later, you can output the size of a standard adjustable voltage. Follower used MAX494, the PCB design, circuit lead to reduced interference, better to MAX494 OPAMP MAX547 input directly connected to the input reference voltage, shown in Figure 4. In addition to reduce the D / A converter ladder caused by high frequency wave
By adjusting the Ral7, Ral8 and Ral9 size, get a larger resistance. However, the process of debugging, we have observed for the measurement time extension Shuchurengran Hui moved to saturation, for which we took advantage of a first-order part with Xiang Ji Fen out the output of the DC component, feedback to Ral9 the end, the formation of self Gensui Network , as shown in the left portion of Figure 2. Use to select the integration capacitor leakage current is relatively small, drift is small, relatively stable performance of the capacitor, the amplifier to select the high gain, high input impedance, low bias current, low drift operational amplifiers, can guarantee the performance of the charge amplifier.
In the application of active vibration control real interest to the signal frequencies are in between 0.5 ~ 200Hz, In order to filter low-frequency drift and unnecessary high-frequency signal, we design a five-order Bessel (Bessel) Di Tong Hu a first-order high-pass band-pass filter composed of five order Bessel low pass it by two second-order low-pass and a first-order low-pass form, their parameters are: passband gain of a cut-off frequency of 475Hz , Q value of 0.577; pass band gain of a cut-off frequency of 565Hz, Q values of O. 737; pass band gain of a cut-off frequency of 530Hz, one, two second-order low-pass circuit by the unity gain KRC. ??? Signal into the DSP's ADC should be preceded by the addition circuit to adjust the ratio to between 0 ~ 3V, 0V, or lower than 3V DSP have damaged the danger of this we have added a limit protection circuit
In this paper, MAX547 as the core component of the F2812 design and implementation of the D / A converter circuit. MAX547-house contains eight 13-bit voltage output D / A converters have an input before each DAC latch and the DAC latch, can be separately gated, to 8 D / A converter. Two DAC per share a reference voltage, a total of four independent external reference voltage. MAX547 interface signal has three address lines, respectively, eight-channel addressing options, 13-bit data line, a chip select / CS, Write / WR, asynchronous input / LD and clear / CLR and other control signals, control signals are level triggered. These interface signals are with the TTL / CMOS level matching, it directly with the MAX547 F2812 connected without the need for level translation. MAX547 is a ± 5V dual supply, the output voltage swing of -4.5 V ~ 4.5V. ??? When the MAX547's write signal / WR and the chip select signal / CS are low, and A0, A1, A2 Address signal is valid, the corresponding channel input latch open, read the conversion values from the data line , when / WR, and / CS goes high one, the data will be locked into the corresponding input latch. / LD is responsible for switching DAC latch, when the / LD is low, DAC latch open, the data from the input latch into the DAC latch, when the / LD becomes high, the data will be maintained in DAC Latch device, the count by the DAC to analog conversion. When / LD, / WR and / CS are low, the data can be directly transmitted to DAC latch, but the / LD should be higher than / WR high inversion delay 50ns. / CLR, you can convert the contents of the DAC is set to 1000H, AGND to the analog output voltage. ??? F2812 has the external interface (XINTF), can the image of five independent external storage space, each storage space has a chip select signal. 8 channels to MAX54.7 address assignment in an external storage area 0, through an external interface bus connection with the F2812 shown in Figure 4. To start the MAX547 internal DACA, DACB, DACC, DACD, DACE, DACF, DACG, DACH carry out a number - analog conversion, respectively, to address D9H, B2H, B3H, F4H, F5H, 7EH, 7FH write the data that need to be converted be. For MAX547AEQH need four independent reference voltage, the system uses a precision voltage reference provides a standard chip REF02 voltage, after four buffered voltage follower. REF02 5V output standard voltage, after conversion later, you can output the size of a standard adjustable voltage. Follower used MAX494, the PCB design, circuit lead to reduced interference, better to MAX494 OPAMP MAX547 input directly connected to the input reference voltage, shown in Figure 4. In addition to reduce the D / A converter ladder caused by high frequency wave
2010年5月12日星期三
PA04 datasheet
PA04 APEX U.S. produced a high-current power amplifier, which has high operating voltage, output current, high slew rate, and low distortion. By combining with the pin of the device characteristics and typical applications, introduces the working principle of PA04 and selected peripheral devices should pay attention to some problems. PA04 for the high current power amplifier. Because of its relatively large output current, which in ordinary settings, and use many different power amplifiers. Here on the working principle of PA04 and its external circuit in the application of issues needing attention and introduced the principles to do something. 2.1-limiting and current limiting resistor PA04 pin 10 and pin 11 for the current feedback input connection circuit shown in Figure 2, the figure, the pin 11 and the amplifier output directly connected to pin 10 and limiting resistor connection. The benefits of such connections can bypass any other parasitic resistance. Limiting resistor must be connected to the position shown in Figure 2. Its size can be calculated by: RCL = 0.76/ILIMIT 2.2 Sleep works Work in sleep mode, PA04 pin 12 and pin 9 connected, the internal amplifier to stop working, then the amplifier will be in hibernation. Sleeping approximately 3mA of current flow through the pin 12. Sleep mode when not in use, should pin 12 floating. There are many dormant circuit, shown in Figure 3 is a sleep circuit. Left logic circuits for the differential mode signal input signal using the transistor conduction and cut-off characteristics can be realized pin 9 and pin 12 is disconnected or connection control. 2.3 Enhanced input PA04 pin 5 and pin 9 to enhance the voltage input (VBOOST) feet, with increased voltage input pin of amplifier For most of the work in the high pressure with little in the high current state. Therefore, + VBOOST pin (pin 9) and-VBOOST pin (pin 5) is generally connected to the amplifier's small signal circuit, + Vs (pin 8) and-Vs (pin 6) was connected to a large current output. When the required output voltage is close to the power supply voltage (ie, lowering the pressure drop), can be applied in VBOOST pin 5V voltage (VBOOST = VS +5) to make the small-signal driving the output transistor saturation At the same time it can also improve the output voltage fluctuations. If you need to improve the output voltage fluctuations, + VBOOST pin and + Vs pin,-VBOOST pin to pin and-Vs are connected together, and certainly not VBOOST pin voltage lower than the Vs pin voltage. VBOOST = VS and VBOOST = VS +5 floating when the output voltage and output current relationship shown in Figure 4.
2010年5月11日星期二
SJA1000 datasheet
Back to back MOSFET, Q1-A and Q1-B have received the V (IN1) (5V) power supply, while Q3-A and Q3-B receives V (IN2) (3.3V) power supply. Use back to back because the MOSFET, the internal diode to prevent the 5V and 3.3V power supply with short circuit. The Gate1 LTC1645 pin control Q3-A and Q3-B, Gate2 pin control Q1-A and Q1-B. ON pin Gate1 conduction threshold voltage of 0.8V, on Gate2 conduction threshold voltage of 2.0V. V (CC1), and V (CC2) pin under-voltage lockout threshold was 2.3V, and 1.2V. Because the circuit is shown in Figure 1, two power supply voltages, so there may occur the following two situations: ? Figure 1: LTC1645 and SJA1000 (using SEPIC converter) constitute the 3.3V and 5V hot swap circuit - Case 1: providing 5V and 3.3V power supply - When the 5V and 3.3V supply voltage were added to V (IN1) and V (IN2) when, D1 to V (CC1), V (CC2), Sense1 and Sense2 pin pulled about 4.7V, is used to remove V (CC1) and V (CC2) of the undervoltage lockout threshold. COMP (+) pin is composed of voltage divider R2 and R6 pulled 2.5V. Because COMP (+) pin voltage (internal comparator inverting input) than the threshold voltage of 1.24V high, so COMPOUT pin (open-drain comparator output) is R7 pulled 5V. This gives the Q5 turns on, and Q3-A and Q3-B of the gate down to the ground. ON pin is R1, R4 and R8 pulled around 2.74V. In a working cycle (t = C2 �� 1.24V/2��A), the internal 10��A from the charge pump power source received Gate1 and Gate2 pin. Gate1 down to the ground pin is Q5, and Gate2 pin voltage begins to rise, the slope of the provisions of the dV / dt = 10��A/C1. Internal charge pump guarantees Gate2 pin voltage rises to about 12V. When Gate2 pin up to 1V or so, Q1-A and Q1-B began to turn, and V (OUT_HOT_SWAP) started to rise. Output voltage will steadily increase the input voltage, here is 5V. Figure 2 shows the Gate2 respectively, and V (OUT_HOT_SWAP) pin voltage up to 12V and 5V respectively, when the characteristic curve.
2010年5月10日星期一
AT89C5131
The mobile storage device with USB2.0 controller chip AT89C5131 TI Corporation, the data storage medium with SAMSUNG's NAND FLASH chip K9K2G08U0A. 2.1 AT89C5131 chip features ATMEL AT89C51-12QC is produced by high-performance core based on 80C52 full speed USB controller built-in 8-bit single CPU micro-processing chip [2], directly compatible with MCS-51 series, its internal integrated 32KB of Flash memory, available in the IN-System Programming; built-in 4KB EEPROM, which 1KB for user data storage, with a control port, and six general programmable ports, and supports control transfer, synchronous transmission, interruption of transmission and bulk transfer of four transfers way. The chip has the advantage of developers familiar with the structure and instruction set, processing ability, constitute the system of the circuit is simple, convenient debugging. 2.2 K9K2G08U0A chip features K9K2G08U0A total capacity of the memory chip (256M +8192 k) bit * 8bit, 2048 is divided into sectors, each sector is divided into 64 pages, each page in addition to 2k bytes of main storage area, but also include 64 spare bytes [3]. It 200μs / complete 2112-byte page programming operation; also completed 128k bytes in 2ms erase operation; while randomly reading time is 25μs; data lines and address lines multiplexed to I/O0-I/O7 A total of eight lines; also provides a command-control signals are line; data retention for more than 10 years. NAND FLASH memory will not increase the storage capacity increases the number of pins, which greatly facilitate the system design and product upgrading, but the chip connection methods and programming to access the same memory than the traditional big difference there. 2.3 Hardware Schematic The hardware part of the built-in USB controller, microcontroller AT89C5131, SAMSUNG's NAND FLASH chip K9K2G08U0A composition, hardware schematics shown in Figure 1. Must write the corresponding command to the successful implementation of the various flash memory operation, because the data lines and address lines multiplexed to eight lines, the address, command and data input / output through the command latch signal (CLE) and address of the lock survival signal (ALE) to jointly control the time division multiplexing. I / O [7:0]: Data I / O port, the signal and AT89C5131 chips P0 [7:0] connection. : Write enable signal. In its rising edge, the command, address and data latched to the corresponding register. The signal and AT89C5131 chips P3.6 signal connections. : Read enable signal. In its falling edge, the output data to I / O bus, the same time, it can accumulate on the internal data address. The signal and AT89C5131 chips P3.7 signal connection. CLE: Command latch enable signal. When CLE is high, the command in rising through the I / O port into the command register. The signal and AT89C5131 chips P1.0 pin connection. ALE: Address latch enable signal. When ALE is high, the address into the address register at the rising edge. The signal and AT89C5131 chips P1.1 pin connection. : Chip select signal. Used to control equipment selection. When the device is busy is high and is ignored, when in device programming and erase operations can not return to standby. The signal and AT89C5131 chips P1.2 pin connection. R /: ready / busy output. When it is low, said the program, erase and random read operation is in progress, the operation is completed and returned to high; when the chip select or output not being prohibited, their time is high. The signal and AT89C5131 chips P1.3 pin connection.
订阅：
博文 (Atom)
